Timer0 Interrupt with PIC Microcontroller

Interrupts in microcontrollers are used when an event or piece of software needs to be implemented and repeated within a fixed duration or when an hardware event occurs. Interrupts can be edge triggered or timer triggered. Edge triggered interrupts are usually activated by the rising or falling edge of a pin connected to the microcontroller. They are used when a software event is expected to occur following an hardware event such as a button press. Timer triggered interrupts, on the other hand, are activated when an event needs to be implemented and completed at a predetermined time period or frequency. Timer interrupts have a number of applications especially in control systems 

Interrupts in PIC16 microcontrollers are Timer0, Timer1 and Timer2 interrupts. We would be focusing on the Timer0 interrupt in an 8-bit PIC16 microcontroller.

In this tutorial, we would perform the task of conguring the Timer0 interrupt to be triggered every 50ms, that is, at a frequency of 20Hz. There are three registers that need to be written into to congure a PIC microcontroller for Timer0 interrupt. These are the OPTION REG, INTCON and TMR0 Registers. 

OPTION REG Register

The OPTION REG Register is an 8-bit Register that contains the bits as shown in Table 1.

As shown in row 3 of Table 1, bit 5 (TOCS) is cleared: the timer mode is selected by clearing bit TOCS. Bit 3 (PSA) is cleared: this means prescaler is assigned to the Timer0 module. Bits2:0 (PS2 : PS0) are the prescaler rate select bits. Bits PS2 : PS0 = 111 means the TMR0 prescaler rate is 1:256. Therefore, the code is:

INTCON Register

The INTCON Register contains various enable and flag bits for the

TMRO register overflow. As shown in Table 2, bit 7 and bit 5 are set. Timer0 interrupt can be enabled/disabled by setting/clearing the TMR0IE enable bit.

GIE = 1 enables all unmasked interrupts

TMR0IE = 1 enables the TMR0 interrupt

Therefore, the code is given as:

TMR0 Register

The TMR0 Register is the Timer0 module register. The TMR0 interrupt is generated when the TMR0 register overf;ows from FFh to 00h. The overflow sets bit TMR0IF(INTCON < 2 >). The interrupt can be masked by clearing bit TMR0IE. TMR0IF must be cleared in software by the Timer0 module ISR (Interrupt Service Routine) before re-enabling this interrupt. The TMR0 interrupt cannot awaken the processor from sleep since the timer is shut o during sleep.

An overflow (FFh to 00h) in the TMR0 register will set the TMR0IF flag bit.

The value written into the TMR0 register determines the timer period at which the interrupt will occur. The formula is given as:

FOSC is the frequency of oscillation, which is given by the frequency of the crystal oscillator, we choose a value of 4MHz.

We want a period of 50ms.

The prescaler is set to 256 in the OPTION REG Register.

Therefore, the calculation is given as:

Therefore, 61 is written into the TMRO register. The hexadecimal value of 61 is 0x3d. Therefore, the code is: