How to Connect LED (Current Source and Sink)

A Light Emitting Diode (LED) can be connected in either way as shown the the following diagrams:

When connecting an LED to a microcontroller, a current source or current sink configuration can be followed.

For Current Source configuration, the LED output is sourcing current so it flowing out of the microcontroller output. In this case, the LED is connected between the GND and the microcontroller output pin. This means that the LED will be switched ON when the microcontroller output is HIGH and switched OFF when the microcontroller output is LOW. This is as shown below, D13 is represented by a pin on the microcontroller.

For a Current Sink Configuration shown below, the LED output is sinking current since it is flowing into the microcontroller output. Tn this case, the LED is connected between the positive supply and the microcontroller output. This means that the LED will be switched ON when the microcontroller output is LOW, and will be switched OFF when the microcontroller output is HIGH.

To determine the value of the current limiting resistor to use, the formula bellow is used:

Where Vcc is the supply voltage; Vf is the LED forward voltage and I is the LED forward current. Vf and I are given in the datasheet of the LED. Therefore, if a supply voltage of 5V is to be used and Vf=1.5V; I = 10mA, the current limiting resistor to be connected will be given by

DC Barrel Power Jack Socket Pinout

This is a common barrel-type power jack for DC wall supplies. Its pinout is as shown in the figure below.

How to Connect LCD to the Arduino

A Liquid Crystal display is connected as follows. D12, D11, D5 - D2 pins as shown in the figure above corresponds to pins 12, 11, 5 - 4 pins on the Arduino. For the VEE pin, a 10KOhm potentiometer can be used instead. For a 16-pin LCD, the A pin is connected to 5v while the K pin is connected to GND. It is optional to connect the A and K pins as they are used for the backlight of the LCD.

TBPDANS001PGUCV Pressure Sensor

The TBPDANS Pressure Sensor is a range of pressure sensor that comes in different pressure range, i.e. from 0 - 1psi; 0 - 5psi; 0 - 100psi, etc. The sensor contains a Wheatstone bridge  and the voltage between the Vout- and Vout+ pins has to measured.

If an Arduino microcontroller is to be used with this sensor, two analog input pins has to be used to measure Vout_ and Vout+ and the difference between these readings will give the voltage as a function of the pressure. But this result of subtracting Vout-  from Vout+ is in the order of 0.1millivolts and therefore the reading will not be evident when using the Arduino because the Arduino uses 10-bit ADC and so the sensitivity for 5v reference is:

This clearly is insufficient as we need a sensitivity less than 0.1mV. If the reference voltage is changed to 3.3v by connecting the AREF pin to 3.3v and writing the code below in the void setup() function:

void setup () {
analogRefence(EXTERNAL); // use AREF for reference voltage
}

This is also inadequate for our use

Also using the 1.1v internal reference of the Arduino by adding the code:

void setup () {

analogRefence(INTERNAL);    // use 1.1v internal reference voltage

}

This resolution is quite good but it should be noted that the using a full scale voltage of 1.1v will result in the maximum voltage that can be measured to be 1.1v. This implies that careful selection as to be made to the supply voltage given to the pressure sensor. The typical supply voltage according to the datasheet is 5v; minimum is 1.5v; maximum is 12v. If a voltage of 5v is applied to the Vcc pin of the pressure sensor, the voltage on the Vout- pin will be the supply voltage divided by 2, i.e. 2.5v while the voltage on the Vout+ pin will be 2.5v plus millivolt changes as the pressure changes.

Therefore using a 1.1v full scale reference will be inadequate, because although we have a higher sensitivity, we cannot measure voltages above 2.5v. 

The solution might be to lower the supply voltage to the pressure sensor. A better solution is to use an op-amp to amplify the voltage to the range the Arduino can measure. INA125 op amp can be used for this. Another better solution is to use a higher ADC bit IC such as a 12-bit ADC or 16-bit ADC or 24-bit ADC.

An example code to read the voltage from the TBPDANS005PGUCV sensor is:

int sensorValue1 = 0;

int sensorValue2 = 0;

float Voutminus;

float Voutplus;

float Vout;

void setup() {

     analogReference(EXTERNAL); // connect AREF pin to the reference voltage being used

                                      // analogReference(INTERNAL) can be used for 1.1v reference on Arduino Uno

     Serial.begin(9600);  

}

void loop() {

 

    sensorValue1 = analogRead(A0);

    sensorValue2 = analogRead(A1);

   

    Voutminus  = (analogRead(A0) * 5000.00) / 1023;   // Voltage in mV

    Voutplus = (analogRead(A1) * 5000.00) / 1023;         // Voltage in mV

    Vout = Voutplus – Voutminus;

    Serial.println(sensorValue1);

    Serial.println(sensorValue2);

    Serial.println(“Vout: ”, Vout, “mV”);

    Serial.println();

   

    delay(2000);          

}

Programming the ASDXACX100PAAA05 pressure sensor

The ASDXACX100PAAA05 pressure sensor is an absolute pressure sensor, that is it measures atmospheric pressure plus any other pressure in the system.

• Maximum pressure, Pmax is 100psi. Minimum pressure, Pmin is 0psi
• Power supply is +5V
• Supply current is 2.5mA
• It uses 10% - 90% calibration
• It uses 12-bit analogue output

Pinout: It has 8 pins, three are used, the remaining are not connected

Arduino uses 10-bit ADC (0 - 1023). Therefore the output voltage from the Arduino is in the range og 0 - 1023. Hence, must be converted to its voltage form. This is achieved by mapping 0 1 1023 to 0 - 5v as shown by the equation below.

Reading the voltage from Arduino: The transfer function limits define the output of the sensor at a given pressure input. By specifying the output signal at the maximum (Pmax) and minimum (Pmin) limit of the pressure range, the complete transfer curve for the sensor is defined.
It uses 10% - 90% of the supply voltage and maps it to Pmin and Pmax respectively. That is:

• At 10% of Vsupply (0.5v), Pmin equals 0psi
• At 90% of Vsupply (4.5v), Pmax equals 100psi

Pmax = maximum limit of pressure range = 100psi
Pmin= minimum limit of pressure range = 0psi

The equation of the transfer function is:

Therefore, at atmospheric pressure (14.696psi), output voltage should equal:

Therefore, pressure applied equals:

The Arduino Code:

/*

 Reads an analog input pin, converts it to voltage and calculates the corresponding output pressure

 Also prints the results to the serial monitor.

 The circuit:

 * ASDX pressure sensor pin 2 connected to analog pin 0.

   pin 1 connected to Vcc (+5v for ASDXACX100PAAA05)

   pin 3 connected to GND

   the other pins are not connected

 * 

 created 15 July. 2014

 by Toria Olawumi

 */

const int ADCFULLSCALE = 1023;               // ADC full scale of arduino is 10-bit (0-1023)

const float reference_voltage_mv = 5000.0;   // Vcc is 5000mv (5V) for ASDXACX100PAAA05

const int Pmax = 100;                       // 100psi for ASDXACX100PAAA05

const int Pmin = 0;                         // 0 psi FOR ASDXACX100PAAA05

const int analogInPin = A0;     // Analog input pin that the asdx pressure sensor is attached to

int sensorValue = 0;           // value read from the pressure sensor

float voltage_mv = 0.0;         // pressure sensor voltage in mV

float voltage_v = 0.0;         // pressure sensor voltage in volts

float output_pressure = 0.0;   // output pressure in psi

float vacuum_pressure = 0.0;   // (substract atmospheric pressure from output_preesure) // vacuum pressure in psi

void setup() {

    Serial.begin(9600); 

}

void loop() {

  // read the analog in value:

  sensorValue = analogRead(analogInPin);                              // digital value of pressure sensor voltage

  voltage_mv =  (sensorValue * reference_voltage_mv) / ADCFULLSCALE;   // pressure sensor voltage in mV

  voltage_v = voltage_mv / 1000;

  Serial.println(voltage_v);

  output_pressure = ( ( (voltage_v - (0.10 * (reference_voltage_mv/1000) )) * (Pmax - Pmin) ) / (0.8 * (reference_voltage_mv/1000) ) ) + Pmin;

  vacuum_pressure = output_pressure - 14.6; // subtract atmospheric pressure

}

Building Simulation Models

Modelling can be considered as the abstract representation of a real world system. For a simulation model, the representation should be executable within a simulation environment to analyse the modelled system with respect to modelling objectives [Changho, 2012].

Modular software systems are written in languages that conceal the distinction between libraries and application programs, software libraries are linked to client programs dynamically at execution time. In modular systems, linking occurs at the time of loading and therefore invisible to the user. Such dynamic linking usually implies that at most one copy of any library module exists in memory at a given time, although several client modules may use it concurrently [Franz, 1997].

Visual C++ can be used for developing the DLL for the simulation model because it allows for the rapid prototyping of an application [Whipple, 1999] by using class library concept to develop behavioural models of electronic components [Kenjo, 2001]. SystemC platform would be another solution because it provides the modelling constructs for high level behavioural models, gate level design, mixed C++ and HDL simulations links. TestBuilder platform could be used as a verification library because it provides transaction level modelling features, constrained randomization and automated signal mapping between C++ signals and HDL signals.

References

Changho, S. Tag, G. (2012), Collaborative Modeling Process for Development of Domain-Specific Discrete Event Simulation Systems, IEEE Transactions on Systems, Man and Cybernetics, Volume 42,  Issue 4, pp 532 - 546, ISSN: 1094-6977

Franz, M. (1997), Dynamic linking of software components, Computer  Volume 30,  Issue 3, pp 74 - 81, ISSN: 0018-9162

Whipple, W. L. (1996), Walking Through an Application with Visual C++, May, 1996, pp 359 – 364, ISBN: 0-7803-327 1-7.

Kenjo,T. Kikuchi,T. and Kubo, M. (2001), Developing Educational Software for Mechatronics Simulation, IEEE Transactions on Education, Volume. 44, No. 2, May 2001, pp 359 – 374, ISSN: 0018–9359.

Proteus ISIS software program

Computer simulation involves designing a model of an actual or theoretical physical system, executing the model on a digital computer and analysing the execution output. An electronic simulator, such as ISIS, can be defined as a program that allows for the drawing of schematic circuits and through mathematical models libraries associated with devices, also permit the simulation of components behaviour in accordance with the global behaviour of the circuit. The software simulation often represent an important part of a development environment that provides important tools as routing software, PCB editor (ARES), a design rule checker and so on.

ISIS makes use of SPICE for the simulation. SPICE, an algorithm developed at University of California, Berkeley represents the core of software electronic simulation. Together with PCB editor tools, SPICE simulation has become the standard in electronics industry for speeding up large-scale production. Integrated Development Environments (IDEs) are required together with electronic circuit design tools for writing program codes to test and simulate the operation of the microcontroller before manufacture of the hardware prototype.

Serial Communication Interface of ER400TRS

The growth of wireless communication technologies since it came into existence in 1901 [Razavi, 1996] prompted the emergence of multitude of new applications and standards [Morgado, 2007].  One of such standards includes the use of Radio Frequency (RF) waves such as that in the ER400 modules which consists of a transmitter, receiver and transceiver. Tracking data from a remote location requires wireless solutions. Cables or infrared signals when used could be tedious and cumbersome. If infrared signals or other optical means including lasers are used, good obstacle-free line of sight or expensive and delicate optical fibres would be required. Thus the solution stays in the RF domain such as the 433MHz frequency channel (the license-free ISM band in Europe). ER400TRS can be interfaced with a microcontroller to transmit data between two remote locations.

The Easy-Radio employs radio waves to communicate over air and use serial communication to connect to a host device (computers or peripherals) which implies that it could act as a RF device as well as a serial device. Serial transmission could be defined as the sequential transmission of characters in a sequence over a single line, rather than simultaneously over two or more lines, as in parallel transmission. This serial transmission of UART (Universal Asynchronous Receiver/Transmitter) depends on the mode, whether in synchronous or asynchronous operation. For synchronous data transmission,  a separate clock signal would be used for synchronising the transmitter and receiver clocks while asynchronous makes use of signal edges (start, data and stop bits) for synchronisation.  The data bits of the ER400 modules are Manchester encoded. Manchester encoded bits are characterized by the presence of a zero crossing in the centre of every bit period. This property permits both low cost timing recovery and very fast start-up from a no signal condition [Ducar, 1981].

For handling the serial communication, a digital component, called the UART is required. Gordon Bell invented the UART when he needed some circuitry to connect a Teletype to a PDP‑1, a task that required converting parallel signals into serial signals and vice versa [Santo, 2009]. Although UART would be needed to send and receive serial data, software alone can do this, a process commonly referred to as bit bang [Ganssle, 1999]. UART can be made to operate in either full duplex or half duplex. Full duplex can be defined by the ability of a UART to simultaneously send and receive data. Half duplex would occur when a device must pause either transmit or receive to perform the other. While most microcontroller UARTs are full duplex, most wireless transceivers such as the ER400TRS are half duplex due to the fact that difficulty could arise when two different signals are sent at the same time under the same frequency causing data collision. VHDL as a design language was used in [Fang, 2011] to achieve the transmitter, receiver and baud rate modules of a UART with stable and reliable results.

Serial communication standards such as the RS232 specification which define the physical layer specify other voltage levels as those provided by UARTs, are commonly implemented as Transistor-Transistor Logic (TTL) or Complementary Metal-Oxide-Semiconductor (CMOS) type digital circuits. In order to convert from the TTL/CMOS levels to the required voltage levels on the medium and provide additional amplification, electrical components called line drivers are used; examples of such driver components are the MAX232 Integrated Circuit [Guoxin, 2010].

References

Razavi, B. (1996), Challenges in Portable RF Transceiver Design, IEEE Circuits and Systems Soceity, pp 12 – 25, ISSN: 8755-3996.

Morgado, A. Rivas, V. J. Rio, R. Castro-Lopez, R. Fernandez, F. V. Rosa, J. M. (2007), Behavioural modelling, simulation and synthesis of multi-standard wireless receivers in MATLAB/SIMULINK, Integration, the VLSI journal, Volume 41, pp 269 – 280, ISSN: 0167-9260.

Ducar, R. (1981), Tevatron Serial Data Repeater System, IEEE Transactions on Nuclear Science, Volume 28, Issue 3, pp 2301 - 2302, ISSN: 0018-9499

Santo, B. (2009), 25 microchips that shook the world, IEEE Spectrum, Volume 46 Issue 5, May 2009, pp 34 - 43 ISSN: 0018-9235.

Ganssle, (1999), Bit Banging, Available: http://www.ganssle.com/articles/auart.htm.

Fang, Y. Chen, X. (2011), Design and Simulation of UART Serial Communication Module Based on VHDL, International Workshop on Intelligent Systems and Applications, pp 1 - 4, ISBN: 978-1-4244-9855-0

Guoxin, L. (2010), Wireless transmission of RS232 interface signal based on ZigBee, International Conference on Anti-Counterfeiting Security and Identification in Communication (ASID), July 2010, pp 239 - 241, ISBN: 978-1-4244-6731-0

Virtual Simulation Modelling of Electronic Components

Virtual modelling systems are aimed at simulating real experimental operation and results by means of computer technology [Yang, 2009]. Due to the huge complexity of modern integrated circuits, computer aided circuit analysis and simulation becomes essential and can provide information about circuit performance that makes it weighty and expensive to do with laboratory prototype measurements. Simulation Program with Integrated Circuit Emphasis (SPICE) was created in order to meet the need for accurate modelling of advanced devices [Senapati, 2002]. SPICE simulation has been used for over thirty years to accurately predict the behaviour of electronic circuits [National Instruments, 2012].

Although it could be difficult to build a digital model to exactly represent the behaviour of an actual device under all operating conditions [Macminn, 1986], software packages such as Proteus ISIS can to a large extent model IC devices using C++ programming language. C++ can be used for building simulation and synthesis models at higher levels of abstraction than other languages. System architects and verification engineers build C++ models of hardware systems for architectural exploration, fast prototyping, hardware/software co-design. Often these C++ based models need to express hardware concepts such as concurrency, structural hierarchy and data types. In the transition of C++ from a software programming language to a language for high level modelling of micro-electronic systems, various artefacts were introduced into the language in the form of library elements to express such hardware concepts [Doucet, 2011]. Engineers can quickly build behavioural models using data structures like queues and associative arrays that mimic the functionality of many hardware components without incurring the cost in memory and simulation time of an equivalent HDL behavioural model. Since C++ designs contains a very rich set of language constructs including the memory and runtime required to create models [Haldar, 2008], Apart from hardware software co-design, the C++ model act as an executable specification to the designed hardware and helped in exploring various design options for the hardware and therefore can be used to prove that the designed hardware was equivalent to the C++ software model [Haldar, 2008]. There are several different embodiments of C++ based environments, mostly in the form of hardware modelling libraries built on top of C++ [Doucet, 2011] such as Visual C++.

Circuit simulation softwares has been widely used by the electrical engineering technologists to study the transients of a power system [Xin, 2012] such as lightning-induced voltage calculations [Montano, 2008]. [Munshi, 2004] modelled the effects of metal shorting, energy storage at metal discontinuities and arbitrary polarity sequence of fingers on a surface acoustic wave inter-digital transducer using C++ program. The model proposed made the SAW device amenable to circuit simulation. A mathematical model and a simulation algorithm based on SPICE was proposed in [Yang, 2009] for a virtual experiment system to simulate real experiment via abstracting experiment scenes, instrument objects and element objects from actual experiment and mathematical and solid model with object-oriented method were constructed. Test results showed that the model achieved excellent performance.

References

Senapati, B. and Maiti, C. K. (2002), Advanced SPICE modelling of SiGe HBTs using VBIC model, IEE proceedings – Circuits, Devices and Systems, Volume 149, Issue 2, pp 129 – 135, ISSN: 1350-2409.

Yang, Y. Zhang, L. Zheng, H. (2009), Research on modelling and simulation in virtual experiment system, International Conference on Computer Science & Education, pp 1090 - 1094, ISBN: 978-1-4244-3520-3.

National Instruments, 2012, SPICE Simulation Overview, Available: http://www.ni.com/white-paper/5414/en.

Macminn, S. R. and Thomas R. J. (1986), Microprocessor simulation of synchronous machine dynamics In real-time, IEEE Transactions on Power Systems, Vol. PWRS-I, No. 3, August 1986, pp 220 – 225, ISSN: 0885-8950.

Doucet, F. Gupta, R. Otsuka, M. Schaumont, P. and Shukla, P. (2001), interoperability as a Design Issue in C++ Based Modelling Environments, International Symposium on System Synthesis, pp 87 – 94, ISBN: 1-58113-418-5.

Haldar, M. Singh, G. Prabhakar, S. Dwivedi, B. Ghosh, A. (2008), Construction of Concrete Verification Models from C ++, IEEE Design Automation Conference, June 2008, pp 942 – 927, ISBN:978-1-60558-115-6

Xin, L. Xiang, C. Lei, Q. (2012), Calculation of Lightning Induced Overvoltages on Overhead Lines Based on DEPACT Macromodel Using Circuit Simulation Software,  IEEE Transactions on Electromagnetic Compatibility, Volume 54,  Issue 4, pp 837 - 849, ISSN: 0018-9375.

Montano, R. Theethayi, N. Cooray, V. (2008), An Efficient Implementation of the Agrawal Model for Lightning Induced Voltage Calculations Using Circuit Simulation Software, IEEE Transactions on Circuits and Systems, Volume 55,  Issue 9, pp 2959 - 2965, ISSN: 1549-8328

Munshi, J. Tuli, S. (2004), A circuit simulation compatible surface acoustic wave interdigital transducer macro-model, IEEE Transactions on Ultrasonics, Ferroelectrics and Frequency Control, Volume 51, Issue 7, pp 782 - 784, ISSN: 0885–3010.

ADC Conversion - Combining ADRESH and ADRESL registers

When writing code for A/D conversion especially using PIC microcontroller, it is often required to read the digital value from the ADRESH and ADRESL registers. Depending on if the ADFM was set to right or left justified, the 10-bit digital value can be obtained.

Right justified is when the 6 MSBs of the ADRESH register are read as '0'
Left justified is when the 6 LSBs of the ADRESL register are read as '0'

For left justified form, 8 bits of the digital value are in the ADRESH register while the remaining 2 bits are in ADRESL register. It is possible to use only the 8-bits from the ADRESH register for left justification while not bothering about the 2 LSBs in the ADRESL register. However, 8-bit resolution of the A/D conversion will be obtained. To obtain a higher resolution (10-bit), the combination can be done by left shifting the contents of the ADRESH register by 2 then right shifting the contents of the ADRESL register by 6 and then perform an OR operation on the result as shown below:

unsigned int x;
unsigned int y;
unsigned int z;

x = ADRESH;
y = ADRESL;
z = (x << 2) | (y >>6);

z now holds a 10-bit number that represents the digital value of the A/D

If right justification is used (ADFM set to 1), a 10-bit A/D value can be obtained by left shifting the contents of the ADRESH register by 6, then right shifting the contents of the ADRESL register by 2, and then perform an OR operation on the result as shown below.

unsigned int x;
unsigned int y;
unsigned int z;

x = ADRESH;
y = ADRESL;
z = (x << 6) | (y >>2);

SRJN (Shortest Remaining Job Next) scheduling algorithm

The SRJN scheduling algorithm uses a fore knowledge of each task execution time and then executives the tasks in the order of their runtime with the short task first. The SRJN scheduling algorithm is fair in the sense that it reduces the time in which shorter tasks have to wait in the system and leaves longer tasks to wait longer in the system. Although the issue of the order in which the processes arrived is not considered in SRJN, it still tries to be fair by ensuring that all the processes are eventually completed. But in the case where a longer job waits for ever because a shorter job always arrives, SRJN can be considered unfair.

The following differences were identified between the SRJN and FCFS scheduling algorithm.
 FCFS executes processes based on the order in which they arrive the processor, the process that requests the CPU first is allocated the CPU first while SRJN executes the processes in accordance with the task that has the shortest time to execute when compared with the other processes.
 In SRJN, the duration time of all the tasks needs to be identified in advance while this is not required in FCFS.
 The average waiting time is higher in FCFS than in SRJN because in FCFS, shorter tasks could be made to wait for longer time if they arrive the CPU late, thereby increasing the overall average wait time. In SRJN, the shortest tasks are completed before the longer ones, thereby reducing the average wait time.
 SRJN is preemptive by releasing the CPU to the next shortest process while in the BLOCKED state while FCFS is non-preemptive.

The following are identified as differences between RR and SRJN
 SRJN only takes into account the task with the shortest time required to complete while RR takes into account the order in which the processes arrives while at the same time giving each process a time slice so that the current process do not have to be completed before the next one can run.
 RR uses a time slice for each process while SRJN does not.
 During CPU intensive processes, the current task must be completed before the next one can run in SRJN; but in RR all tasks are given equal time to run and moves to the nest process even though the current one may not be completed.
 In SRJN, there is a fore knowledge of the runtime of each of the processes which it uses to determine the next process to execute; there is no previous knowledge of the runtime in RR.
 When SRJN is undergoing an IO operation, it becomes more efficient than RR by considering the job that takes the shortest time to complete while RR does not consider.
 The average wait time of RR is higher than that of SRJN because RR tends to make all processes to spend an equal amount of time in the system at the expense of an increased average wait time.
 When undergoing only CPU intensive processes, SRJN becomes faster than RR because the context switch time introduced in RR increases the elapsed time.
 SRJN has the potential of starving longer tasks so that they do not get the chance to run if a job with a considerable shorter time is continuously added.

The following are identified as differences between SJF and SRJN
 The wait time for each of the processes in SRJN is generally shorter than that of SJN, consequently, a lower average wait time is experienced by SRJN.
 The total time for each of the processes in SRJN is shorter than that in SJN.
 SRJN is preemptive because it releases the CPU to the next shortest process while in the BLOCKED state but SJN is non-preemptive (the current process has to complete before the next one can take over).

RR (Round Robin) scheduling algorithm

In terms of the overall effect of the RR scheduling algorithm, it can be considered as a fair algorithm because all processes are allowed to run for a predefined and equal amount of time, which is repeated until they are completed with the shorter process completing faster than a longer one. When fairness is viewed in terms of jobs that arrive first should be completed first, RR scheduling algorithm tries to be fair by giving that process a share of the time first before proceeding to the next process.

The following are identified as differences between RR and FCFS (First Come First Served)
 In FCFS, tasks are performed and completed in accordance with how the process arrives the CPU while RR takes into account the order in which the processes arrives while at the same time giving each process a time slice so that the current process do not have to be completed before the next one can run.
 When FCFS is undergoing an IO operation, it becomes very inefficient as it does not release the CPU to another process (non-preemptive) while RR is a preemptive scheduling algorithm that frees the CPU to the next process when in the BLOCKED state.
 The average wait time of RR is higher than that of FCFS because RR tends to make all processes to spend an equal amount of time in the system at the expense of an increased average wait time.
 When undergoing only CPU intensive processes, FCFS becomes faster than RR because the context switch time introduced in RR increases the elapsed time.

The following are identified as differences between RR and SJF
 In SJF, tasks are performed and completed in accordance with the shortest time it takes to complete a particular process while RR takes into account the order in which the processes arrives while at the same time giving each process a time slice so that the current process do not have to be completed before the next one can run.
 In SJF, there is a fore knowledge of the runtime of each of the processes which it uses to determine the next process to execute; there is no previous knowledge of the runtime in RR.
 When SJF is undergoing an IO operation, it becomes very inefficient as it does not release the CPU to another process (non-preemptive) while RR is a preemptive scheduling algorithm that frees the CPU to the next process when in the BLOCKED state.
 The average wait time of RR is higher than that of SJF because RR tends to make all processes to spend an equal amount of time in the system at the expense of an increased average wait time.
 When undergoing only CPU intensive processes, SJF becomes faster than RR because the context switch time introduced in RR increases the elapsed time.
 SJF has the potential of starving longer tasks so that they do not get the chance to run if a job with a considerable shorter time is continuously added.

SJF (Shortest Job First) Scheduling Algorithm

The SJF scheduling algorithm uses a fore knowledge of each task execution time and then executives the tasks in the order of their runtime with the short task first. The SJF scheduling algorithm is fair in the sense that it reduces the time in which shorter tasks have to wait in the system and leaves longer tasks to wait longer in the system. Although the issue of the order in which the processes arrived is not considered in SJF, it still tries to be fair by ensuring that all the processes are eventually completed. But in the case where a job waits for ever because a shorter job gets called so often thereby preventing its execution even though it arrived first, SJF can be considered unfair.

The following differences were identified between the SJF and FCFS scheduling algorithm.
 FCFS executes processes based on the order in which they arrive the processor, the process that requests the CPU first is allocated the CPU first while SJF executes the processes based on the order of the time it takes to execute each process with the shortest task first.
 In SJF, the duration time of all the tasks needs to be identified in advance while this is not required in FCFS
 The average waiting time is higher in FCFS than in SJF because in FCFS, shorter tasks could be made to wait for longer time if they arrive the CPU late, thereby increasing the overall average wait time. In SJF, the shortest tasks are completed before the longer ones, thereby reducing the average wait time.

FCFS scheduling algorithm

The FCFS algorithm is non preemptive because the algorithm does not permit the release of CPU while the on-going process is in the BLOCKED state but releases the CPU until the current process was completed.

The FCFS scheduling algorithm is fair in that all tasks will definitely get executed and this would be done in the order at which they arrive. Although tasks that arrive early but have long execution time will be done and completed first which keeps those processes with short execution time on hold.

 

The first process is executed first, even though it might have the longest runtime, all other processes have to wait until the process was completed before the next one can start and then the next one. This does not appear very reasonable because those tasks with shorter time should have been allowed to be executed first so that their wait time in the processor would be reduced then the process with the longest execution test can be done last.

Dynamic Priority Scheduling Example

Question: In a real time system four processes A, B, C and D are in a ready queue with the requirements shown in the table below. If a process will not complete within its maximum permitted period the priority changes to 1 where it will execute until finished. Processes should remain at priority level 2 for as long as possible. The clock tick period is 100ms and the context switch period is 1ms. Determine, through the use of a time-slice diagram, if the priority of any of the processes needs to be changed at any time for all of the time slices, for each of the processes determine the total run time and identify whether it meets the timing requirements. Compare results when round-robin scheduling is used.

	A	B	C	D
Total time(ms)	155	160	120	250
Initial priority	2	2	2	2
Max period(ms)	170	550	300	900

Solution:

N(process) = Number of time slots required
R(process) = Number of time slots remaining

Process A: N(A) = 155/100 = 1.6
                 R(A) = 170/101 = 1.7 R(A) ≤ N(A) + 1
Process B: N(B) = 160/100 = 1.6
                 R(B) = 550/101 = 5.5 R(B) ≥ N(B) + 1
Process C:  N(C) = 120/100 = 1.2
                 R(C) = 300/101 = 3.0 R(C) ≥ N(C) + 1
Process D:  N(D) = 250/100 = 2.5
                  R(D) = 900/101 = 9.0 R(D) ≥  N(D) + 1

Process A goes first because is priority is changed to 1

Time Slice 1

Process A: N(A) = 55/100 = 0.6
                 R(A) = 69/101 = 0.7 R(A) ≤ N(A) + 1
Process B: N(B) = 160/100 = 1.6
                 R(B) = 449/101 = 4.4 R(B) ≥ N(B) + 1
Process C:  N(C) = 120/100 = 1.2
                 R(C) = 199/101 = 2.0 R(C) ≤ N(C) + 1
Process D: N(D) = 250/100 = 2.5
                 R(D) = 799/101 = 7.9 R(D) ≥  N(D) + 1

Process A and Process C have their priority changed to 1, since process A was given the previous time slot, process C goes next as the two processes now execute in Round-Robin Scheduling.

Time Slice 2

Process A: N(A) = 55/100 = 0.6
                        R(A) = 69/101 = 0.7 R(A) ≤ N(A) + 1
Process B: N(B) = 160/100 = 1.6
                        R(B) = 348/101 = 3.4 R(B) ≥ N(B) + 1
Process C:         N(C) = 20/100 = 0.2
                        R(C) = 98/101 = 1.0 R(C) ≤ N(C) + 1
Process D:         N(D) = 250/100 = 2.5
                        R(D) = 698/101 = 6.9 R(D) ≥  N(D) + 1

Process A goes next for the next time slice since process A and C have equal priority and process C executed in the previous time slice.

Time Slice 3

Process A:         N(A) = 0/100 = 0

                        R(A) = 13/101 = 0.1 Finished

Process B: N(B) = 160/100 = 1.6

                        R(B) = 292/101 = 2.9 R(B) ≥ N(B) + 1

Process C:         N(C) = 20/100 = 0.2

                        R(C) = 42/101 = 0.4 R(C) ≤ N(C) + 1

Process D:         N(D) = 250/100 = 2.5

                        R(D) = 642/101 = 6.4 R(D) ≥  N(D) + 1

Process A has finished and therefore is removed from the list. Process C now becomes the only task with the highest priority and therefore goes next.

Time Slice 4

Process B: N(B) = 160/100 = 1.6

                        R(B) = 271/101 = 2.7 R(B) ≥ N(B) + 1

Process C:         N(C) = 0/100 = 0

                        R(C) = 21/101 = 0.2 Finished

Process D:         N(D) = 250/100 = 2.5

                        R(D) = 621/101 = 6.1 R(D) ≥  N(D) + 1

Process C has finished and therefore is removed from the list. Process B and D are now left, with the same priority of 2 and will be taken in round robin sequence starting with process B. 

Time Slice 5

Process B: N(B) = 60/100 = 0.6
                        R(B) = 170/101 = 1.7 R(B) ≥ N(B) + 1
Process D:        N(D) = 250/100 = 2.5
                        R(D) = 520/101 = 5.2 R(D) ≥  N(D) + 1

Process D goes next as both processes are taken in round robin scheduling with process B executing in the previous time slice.

Time Slice 6

Process B: N(B) = 60/100 = 0.6

                        R(B) = 69/101 = 0.7 R(B) ≤ N(B) + 1

Process D:        N(D) = 150/100 = 1.5

                        R(D) = 419/101 = 4.2 R(D) ≥  N(D) + 1

Process B becomes a priority and therefore goes next.

Time Slice 7

Process B: N(B) = 0/100 = 0

                       R(B) = 8/101 = 0.1 Finished

Process D:       N(D) = 150/100 = 1.5

                        R(D) = 358/101 = 3.5 R(D) ≥  N(D) + 1

Process B is completed and removed from the list. Only Process D is left and executes until completion in the next time slice.

Time Slice 8 and 9

Therefore, the full time slice diagram is given by:

Total time required for Process A:

100 + 1 + 100 + 1+ 55 = 257ms

Total time required for Process B:

100 + 1 + 100 + 1 + 55 + 1 + 20 + 1 + 100 + 1 + 100 + 1 + 60 = 541ms

Total time required for Process C:

100 + 1 + 100 + 1 + 55 + 1 + 20 = 278ms

Total time required for Process D:

100 + 1 + 100 + 1 + 55 + 1 + 20 + 1 + 100 + 1 + 100 + 1 + 60 + 1 + 100 + 1 + 50 = 693ms

Process B, C and D met their timing requirements while Process A failed to meet its maximum permitted time of 170ms.

Using round robin scheduling, the time slices are as shown

Total time required for Process A:

100 + 1 + 100 + 1+ 100 + 1 + 100 + 1 + 55 = 459ms

Total time required for Process B:

100 + 1 + 100 + 1+ 100 + 1 + 100 + 1 + 55 + 1 + 60 = 520ms

Total time required for Process C:

100 + 1 + 100 + 1+ 100 + 1 + 100 + 1 + 55 + 1 + 60 + 1+ 20 = 541ms

Total time required for Process D:

100 + 1 + 100 + 1+ 100 + 1 + 100 + 1 + 55 + 1 + 60 + 1+ 20 + 1 + 100 + 1 + 50 = 693ms

In round robin scheduling, Process B and D met their maximum permitted time while Process A and C failed to meet their timing requirements.

Interpreting I2C Signal Data

Two signals are as shown in the diagram below. What are the names of the two signals? Determine the data present on the I2C signal below.

Solution

Signal A is the SDA (Serial Data) signal while signal B is the SCL (Serial Clock) signal. A start occurs when the SDA line drops when the SCK is HIGH. Data is read at the rising edge of the clock. An ACK (Acknowledgement) is sent when two byte data have been read. A stop occurs when the SDA line rises when the clock is HIGH. The interpretation is as shown by the diagram below.

Therefore the interpreted I2C signal is A4FA in hexadecimal as represented by the diagram

I2C Bus Pull-up Resistors

If the maximum permitted rise time for both the serial data (SDA) and serial clock (SCL) line of an I2C bus is 1000ns, the load capacitance is 200pF, and the minimum logic high voltage is 3.3V. The maximum acceptable values of the pull-up resistors to be used is calculated as:

Where:
t = Maximum time
C = Load Capacitance
Vth = Minimum logic high voltage
Vcc = Supply Voltage
Vo = Bus line Output Voltage

Therefore, choose a 4.7KΩ resistor as the value of resistor pull-up