Signal A is the SDA (Serial Data) signal while signal B is the SCL (Serial Clock) signal. A start occurs when the SDA line drops when the SCK is HIGH. Data is read at the rising edge of the clock. An ACK (Acknowledgement) is sent when two byte data have been read. A stop occurs when the SDA line rises when the clock is HIGH. The interpretation is as shown by the diagram below.
The stop bit is not identified correctly. It's a rising edge on Data during a clock high.
ReplyDeleteActually, my issue is that the second ack is missing. The last bit and the stop condition don't happen during the same clock cycle.
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