Virtual Simulation Modelling of Electronic Components

Virtual modelling systems are aimed at simulating real experimental operation and results by means of computer technology [Yang, 2009]. Due to the huge complexity of modern integrated circuits, computer aided circuit analysis and simulation becomes essential and can provide information about circuit performance that makes it weighty and expensive to do with laboratory prototype measurements. Simulation Program with Integrated Circuit Emphasis (SPICE) was created in order to meet the need for accurate modelling of advanced devices [Senapati, 2002]. SPICE simulation has been used for over thirty years to accurately predict the behaviour of electronic circuits [National Instruments, 2012].

Although it could be difficult to build a digital model to exactly represent the behaviour of an actual device under all operating conditions [Macminn, 1986], software packages such as Proteus ISIS can to a large extent model IC devices using C++ programming language. C++ can be used for building simulation and synthesis models at higher levels of abstraction than other languages. System architects and verification engineers build C++ models of hardware systems for architectural exploration, fast prototyping, hardware/software co-design. Often these C++ based models need to express hardware concepts such as concurrency, structural hierarchy and data types. In the transition of C++ from a software programming language to a language for high level modelling of micro-electronic systems, various artefacts were introduced into the language in the form of library elements to express such hardware concepts [Doucet, 2011]. Engineers can quickly build behavioural models using data structures like queues and associative arrays that mimic the functionality of many hardware components without incurring the cost in memory and simulation time of an equivalent HDL behavioural model. Since C++ designs contains a very rich set of language constructs including the memory and runtime required to create models [Haldar, 2008], Apart from hardware software co-design, the C++ model act as an executable specification to the designed hardware and helped in exploring various design options for the hardware and therefore can be used to prove that the designed hardware was equivalent to the C++ software model [Haldar, 2008]. There are several different embodiments of C++ based environments, mostly in the form of hardware modelling libraries built on top of C++ [Doucet, 2011] such as Visual C++.

Circuit simulation softwares has been widely used by the electrical engineering technologists to study the transients of a power system [Xin, 2012] such as lightning-induced voltage calculations [Montano, 2008]. [Munshi, 2004] modelled the effects of metal shorting, energy storage at metal discontinuities and arbitrary polarity sequence of fingers on a surface acoustic wave inter-digital transducer using C++ program. The model proposed made the SAW device amenable to circuit simulation. A mathematical model and a simulation algorithm based on SPICE was proposed in [Yang, 2009] for a virtual experiment system to simulate real experiment via abstracting experiment scenes, instrument objects and element objects from actual experiment and mathematical and solid model with object-oriented method were constructed. Test results showed that the model achieved excellent performance.

References

Senapati, B. and Maiti, C. K. (2002), Advanced SPICE modelling of SiGe HBTs using VBIC model, IEE proceedings – Circuits, Devices and Systems, Volume 149, Issue 2, pp 129 – 135, ISSN: 1350-2409.

Yang, Y. Zhang, L. Zheng, H. (2009), Research on modelling and simulation in virtual experiment system, International Conference on Computer Science & Education, pp 1090 - 1094, ISBN: 978-1-4244-3520-3.

National Instruments, 2012, SPICE Simulation Overview, Available: http://www.ni.com/white-paper/5414/en.

Macminn, S. R. and Thomas R. J. (1986), Microprocessor simulation of synchronous machine dynamics In real-time, IEEE Transactions on Power Systems, Vol. PWRS-I, No. 3, August 1986, pp 220 – 225, ISSN: 0885-8950.

Doucet, F. Gupta, R. Otsuka, M. Schaumont, P. and Shukla, P. (2001), interoperability as a Design Issue in C++ Based Modelling Environments, International Symposium on System Synthesis, pp 87 – 94, ISBN: 1-58113-418-5.

Haldar, M. Singh, G. Prabhakar, S. Dwivedi, B. Ghosh, A. (2008), Construction of Concrete Verification Models from C ++, IEEE Design Automation Conference, June 2008, pp 942 – 927, ISBN:978-1-60558-115-6

Xin, L. Xiang, C. Lei, Q. (2012), Calculation of Lightning Induced Overvoltages on Overhead Lines Based on DEPACT Macromodel Using Circuit Simulation Software,  IEEE Transactions on Electromagnetic Compatibility, Volume 54,  Issue 4, pp 837 - 849, ISSN: 0018-9375.

Montano, R. Theethayi, N. Cooray, V. (2008), An Efficient Implementation of the Agrawal Model for Lightning Induced Voltage Calculations Using Circuit Simulation Software, IEEE Transactions on Circuits and Systems, Volume 55,  Issue 9, pp 2959 - 2965, ISSN: 1549-8328

Munshi, J. Tuli, S. (2004), A circuit simulation compatible surface acoustic wave interdigital transducer macro-model, IEEE Transactions on Ultrasonics, Ferroelectrics and Frequency Control, Volume 51, Issue 7, pp 782 - 784, ISSN: 0885–3010.

ADC Conversion - Combining ADRESH and ADRESL registers

When writing code for A/D conversion especially using PIC microcontroller, it is often required to read the digital value from the ADRESH and ADRESL registers. Depending on if the ADFM was set to right or left justified, the 10-bit digital value can be obtained.

Right justified is when the 6 MSBs of the ADRESH register are read as '0'
Left justified is when the 6 LSBs of the ADRESL register are read as '0'

For left justified form, 8 bits of the digital value are in the ADRESH register while the remaining 2 bits are in ADRESL register. It is possible to use only the 8-bits from the ADRESH register for left justification while not bothering about the 2 LSBs in the ADRESL register. However, 8-bit resolution of the A/D conversion will be obtained. To obtain a higher resolution (10-bit), the combination can be done by left shifting the contents of the ADRESH register by 2 then right shifting the contents of the ADRESL register by 6 and then perform an OR operation on the result as shown below:

unsigned int x;
unsigned int y;
unsigned int z;

x = ADRESH;
y = ADRESL;
z = (x << 2) | (y >>6);

z now holds a 10-bit number that represents the digital value of the A/D

If right justification is used (ADFM set to 1), a 10-bit A/D value can be obtained by left shifting the contents of the ADRESH register by 6, then right shifting the contents of the ADRESL register by 2, and then perform an OR operation on the result as shown below.

unsigned int x;
unsigned int y;
unsigned int z;

x = ADRESH;
y = ADRESL;
z = (x << 6) | (y >>2);

SRJN (Shortest Remaining Job Next) scheduling algorithm

The SRJN scheduling algorithm uses a fore knowledge of each task execution time and then executives the tasks in the order of their runtime with the short task first. The SRJN scheduling algorithm is fair in the sense that it reduces the time in which shorter tasks have to wait in the system and leaves longer tasks to wait longer in the system. Although the issue of the order in which the processes arrived is not considered in SRJN, it still tries to be fair by ensuring that all the processes are eventually completed. But in the case where a longer job waits for ever because a shorter job always arrives, SRJN can be considered unfair.

The following differences were identified between the SRJN and FCFS scheduling algorithm.
 FCFS executes processes based on the order in which they arrive the processor, the process that requests the CPU first is allocated the CPU first while SRJN executes the processes in accordance with the task that has the shortest time to execute when compared with the other processes.
 In SRJN, the duration time of all the tasks needs to be identified in advance while this is not required in FCFS.
 The average waiting time is higher in FCFS than in SRJN because in FCFS, shorter tasks could be made to wait for longer time if they arrive the CPU late, thereby increasing the overall average wait time. In SRJN, the shortest tasks are completed before the longer ones, thereby reducing the average wait time.
 SRJN is preemptive by releasing the CPU to the next shortest process while in the BLOCKED state while FCFS is non-preemptive.

The following are identified as differences between RR and SRJN
 SRJN only takes into account the task with the shortest time required to complete while RR takes into account the order in which the processes arrives while at the same time giving each process a time slice so that the current process do not have to be completed before the next one can run.
 RR uses a time slice for each process while SRJN does not.
 During CPU intensive processes, the current task must be completed before the next one can run in SRJN; but in RR all tasks are given equal time to run and moves to the nest process even though the current one may not be completed.
 In SRJN, there is a fore knowledge of the runtime of each of the processes which it uses to determine the next process to execute; there is no previous knowledge of the runtime in RR.
 When SRJN is undergoing an IO operation, it becomes more efficient than RR by considering the job that takes the shortest time to complete while RR does not consider.
 The average wait time of RR is higher than that of SRJN because RR tends to make all processes to spend an equal amount of time in the system at the expense of an increased average wait time.
 When undergoing only CPU intensive processes, SRJN becomes faster than RR because the context switch time introduced in RR increases the elapsed time.
 SRJN has the potential of starving longer tasks so that they do not get the chance to run if a job with a considerable shorter time is continuously added.

The following are identified as differences between SJF and SRJN
 The wait time for each of the processes in SRJN is generally shorter than that of SJN, consequently, a lower average wait time is experienced by SRJN.
 The total time for each of the processes in SRJN is shorter than that in SJN.
 SRJN is preemptive because it releases the CPU to the next shortest process while in the BLOCKED state but SJN is non-preemptive (the current process has to complete before the next one can take over).

RR (Round Robin) scheduling algorithm

In terms of the overall effect of the RR scheduling algorithm, it can be considered as a fair algorithm because all processes are allowed to run for a predefined and equal amount of time, which is repeated until they are completed with the shorter process completing faster than a longer one. When fairness is viewed in terms of jobs that arrive first should be completed first, RR scheduling algorithm tries to be fair by giving that process a share of the time first before proceeding to the next process.

The following are identified as differences between RR and FCFS (First Come First Served)
 In FCFS, tasks are performed and completed in accordance with how the process arrives the CPU while RR takes into account the order in which the processes arrives while at the same time giving each process a time slice so that the current process do not have to be completed before the next one can run.
 When FCFS is undergoing an IO operation, it becomes very inefficient as it does not release the CPU to another process (non-preemptive) while RR is a preemptive scheduling algorithm that frees the CPU to the next process when in the BLOCKED state.
 The average wait time of RR is higher than that of FCFS because RR tends to make all processes to spend an equal amount of time in the system at the expense of an increased average wait time.
 When undergoing only CPU intensive processes, FCFS becomes faster than RR because the context switch time introduced in RR increases the elapsed time.

The following are identified as differences between RR and SJF
 In SJF, tasks are performed and completed in accordance with the shortest time it takes to complete a particular process while RR takes into account the order in which the processes arrives while at the same time giving each process a time slice so that the current process do not have to be completed before the next one can run.
 In SJF, there is a fore knowledge of the runtime of each of the processes which it uses to determine the next process to execute; there is no previous knowledge of the runtime in RR.
 When SJF is undergoing an IO operation, it becomes very inefficient as it does not release the CPU to another process (non-preemptive) while RR is a preemptive scheduling algorithm that frees the CPU to the next process when in the BLOCKED state.
 The average wait time of RR is higher than that of SJF because RR tends to make all processes to spend an equal amount of time in the system at the expense of an increased average wait time.
 When undergoing only CPU intensive processes, SJF becomes faster than RR because the context switch time introduced in RR increases the elapsed time.
 SJF has the potential of starving longer tasks so that they do not get the chance to run if a job with a considerable shorter time is continuously added.

SJF (Shortest Job First) Scheduling Algorithm

The SJF scheduling algorithm uses a fore knowledge of each task execution time and then executives the tasks in the order of their runtime with the short task first. The SJF scheduling algorithm is fair in the sense that it reduces the time in which shorter tasks have to wait in the system and leaves longer tasks to wait longer in the system. Although the issue of the order in which the processes arrived is not considered in SJF, it still tries to be fair by ensuring that all the processes are eventually completed. But in the case where a job waits for ever because a shorter job gets called so often thereby preventing its execution even though it arrived first, SJF can be considered unfair.

The following differences were identified between the SJF and FCFS scheduling algorithm.
 FCFS executes processes based on the order in which they arrive the processor, the process that requests the CPU first is allocated the CPU first while SJF executes the processes based on the order of the time it takes to execute each process with the shortest task first.
 In SJF, the duration time of all the tasks needs to be identified in advance while this is not required in FCFS
 The average waiting time is higher in FCFS than in SJF because in FCFS, shorter tasks could be made to wait for longer time if they arrive the CPU late, thereby increasing the overall average wait time. In SJF, the shortest tasks are completed before the longer ones, thereby reducing the average wait time.

FCFS scheduling algorithm

The FCFS algorithm is non preemptive because the algorithm does not permit the release of CPU while the on-going process is in the BLOCKED state but releases the CPU until the current process was completed.

The FCFS scheduling algorithm is fair in that all tasks will definitely get executed and this would be done in the order at which they arrive. Although tasks that arrive early but have long execution time will be done and completed first which keeps those processes with short execution time on hold.

 

The first process is executed first, even though it might have the longest runtime, all other processes have to wait until the process was completed before the next one can start and then the next one. This does not appear very reasonable because those tasks with shorter time should have been allowed to be executed first so that their wait time in the processor would be reduced then the process with the longest execution test can be done last.

Dynamic Priority Scheduling Example

Question: In a real time system four processes A, B, C and D are in a ready queue with the requirements shown in the table below. If a process will not complete within its maximum permitted period the priority changes to 1 where it will execute until finished. Processes should remain at priority level 2 for as long as possible. The clock tick period is 100ms and the context switch period is 1ms. Determine, through the use of a time-slice diagram, if the priority of any of the processes needs to be changed at any time for all of the time slices, for each of the processes determine the total run time and identify whether it meets the timing requirements. Compare results when round-robin scheduling is used.

	A	B	C	D
Total time(ms)	155	160	120	250
Initial priority	2	2	2	2
Max period(ms)	170	550	300	900

Solution:

N(process) = Number of time slots required
R(process) = Number of time slots remaining

Process A: N(A) = 155/100 = 1.6
                 R(A) = 170/101 = 1.7 R(A) ≤ N(A) + 1
Process B: N(B) = 160/100 = 1.6
                 R(B) = 550/101 = 5.5 R(B) ≥ N(B) + 1
Process C:  N(C) = 120/100 = 1.2
                 R(C) = 300/101 = 3.0 R(C) ≥ N(C) + 1
Process D:  N(D) = 250/100 = 2.5
                  R(D) = 900/101 = 9.0 R(D) ≥  N(D) + 1

Process A goes first because is priority is changed to 1

Time Slice 1

Process A: N(A) = 55/100 = 0.6
                 R(A) = 69/101 = 0.7 R(A) ≤ N(A) + 1
Process B: N(B) = 160/100 = 1.6
                 R(B) = 449/101 = 4.4 R(B) ≥ N(B) + 1
Process C:  N(C) = 120/100 = 1.2
                 R(C) = 199/101 = 2.0 R(C) ≤ N(C) + 1
Process D: N(D) = 250/100 = 2.5
                 R(D) = 799/101 = 7.9 R(D) ≥  N(D) + 1

Process A and Process C have their priority changed to 1, since process A was given the previous time slot, process C goes next as the two processes now execute in Round-Robin Scheduling.

Time Slice 2

Process A: N(A) = 55/100 = 0.6
                        R(A) = 69/101 = 0.7 R(A) ≤ N(A) + 1
Process B: N(B) = 160/100 = 1.6
                        R(B) = 348/101 = 3.4 R(B) ≥ N(B) + 1
Process C:         N(C) = 20/100 = 0.2
                        R(C) = 98/101 = 1.0 R(C) ≤ N(C) + 1
Process D:         N(D) = 250/100 = 2.5
                        R(D) = 698/101 = 6.9 R(D) ≥  N(D) + 1

Process A goes next for the next time slice since process A and C have equal priority and process C executed in the previous time slice.

Time Slice 3

Process A:         N(A) = 0/100 = 0

                        R(A) = 13/101 = 0.1 Finished

Process B: N(B) = 160/100 = 1.6

                        R(B) = 292/101 = 2.9 R(B) ≥ N(B) + 1

Process C:         N(C) = 20/100 = 0.2

                        R(C) = 42/101 = 0.4 R(C) ≤ N(C) + 1

Process D:         N(D) = 250/100 = 2.5

                        R(D) = 642/101 = 6.4 R(D) ≥  N(D) + 1

Process A has finished and therefore is removed from the list. Process C now becomes the only task with the highest priority and therefore goes next.

Time Slice 4

Process B: N(B) = 160/100 = 1.6

                        R(B) = 271/101 = 2.7 R(B) ≥ N(B) + 1

Process C:         N(C) = 0/100 = 0

                        R(C) = 21/101 = 0.2 Finished

Process D:         N(D) = 250/100 = 2.5

                        R(D) = 621/101 = 6.1 R(D) ≥  N(D) + 1

Process C has finished and therefore is removed from the list. Process B and D are now left, with the same priority of 2 and will be taken in round robin sequence starting with process B. 

Time Slice 5

Process B: N(B) = 60/100 = 0.6
                        R(B) = 170/101 = 1.7 R(B) ≥ N(B) + 1
Process D:        N(D) = 250/100 = 2.5
                        R(D) = 520/101 = 5.2 R(D) ≥  N(D) + 1

Process D goes next as both processes are taken in round robin scheduling with process B executing in the previous time slice.

Time Slice 6

Process B: N(B) = 60/100 = 0.6

                        R(B) = 69/101 = 0.7 R(B) ≤ N(B) + 1

Process D:        N(D) = 150/100 = 1.5

                        R(D) = 419/101 = 4.2 R(D) ≥  N(D) + 1

Process B becomes a priority and therefore goes next.

Time Slice 7

Process B: N(B) = 0/100 = 0

                       R(B) = 8/101 = 0.1 Finished

Process D:       N(D) = 150/100 = 1.5

                        R(D) = 358/101 = 3.5 R(D) ≥  N(D) + 1

Process B is completed and removed from the list. Only Process D is left and executes until completion in the next time slice.

Time Slice 8 and 9

Therefore, the full time slice diagram is given by:

Total time required for Process A:

100 + 1 + 100 + 1+ 55 = 257ms

Total time required for Process B:

100 + 1 + 100 + 1 + 55 + 1 + 20 + 1 + 100 + 1 + 100 + 1 + 60 = 541ms

Total time required for Process C:

100 + 1 + 100 + 1 + 55 + 1 + 20 = 278ms

Total time required for Process D:

100 + 1 + 100 + 1 + 55 + 1 + 20 + 1 + 100 + 1 + 100 + 1 + 60 + 1 + 100 + 1 + 50 = 693ms

Process B, C and D met their timing requirements while Process A failed to meet its maximum permitted time of 170ms.

Using round robin scheduling, the time slices are as shown

Total time required for Process A:

100 + 1 + 100 + 1+ 100 + 1 + 100 + 1 + 55 = 459ms

Total time required for Process B:

100 + 1 + 100 + 1+ 100 + 1 + 100 + 1 + 55 + 1 + 60 = 520ms

Total time required for Process C:

100 + 1 + 100 + 1+ 100 + 1 + 100 + 1 + 55 + 1 + 60 + 1+ 20 = 541ms

Total time required for Process D:

100 + 1 + 100 + 1+ 100 + 1 + 100 + 1 + 55 + 1 + 60 + 1+ 20 + 1 + 100 + 1 + 50 = 693ms

In round robin scheduling, Process B and D met their maximum permitted time while Process A and C failed to meet their timing requirements.

Interpreting I2C Signal Data

Two signals are as shown in the diagram below. What are the names of the two signals? Determine the data present on the I2C signal below.

Solution

Signal A is the SDA (Serial Data) signal while signal B is the SCL (Serial Clock) signal. A start occurs when the SDA line drops when the SCK is HIGH. Data is read at the rising edge of the clock. An ACK (Acknowledgement) is sent when two byte data have been read. A stop occurs when the SDA line rises when the clock is HIGH. The interpretation is as shown by the diagram below.

Therefore the interpreted I2C signal is A4FA in hexadecimal as represented by the diagram

I2C Bus Pull-up Resistors

If the maximum permitted rise time for both the serial data (SDA) and serial clock (SCL) line of an I2C bus is 1000ns, the load capacitance is 200pF, and the minimum logic high voltage is 3.3V. The maximum acceptable values of the pull-up resistors to be used is calculated as:

Where:
t = Maximum time
C = Load Capacitance
Vth = Minimum logic high voltage
Vcc = Supply Voltage
Vo = Bus line Output Voltage

Therefore, choose a 4.7KΩ resistor as the value of resistor pull-up

Round robin Scheduling

Four processes A, B, C and D are in a ready queue of a real time operating system. Round robin Scheduling is to be used.
Process A requires 430μS to complete and is executed every 850μS.
Process B requires 200μS to complete and is executed every 700μS.
Process C requires 250μS to complete and is executed every 600μS.
Process D requires 410μS to complete and is executed every 710μS.

The clock tick period is 145μs while the context switch period is 11μs.

Solution
In Round robin Scheduling, each process gets equal time and execution of the processes is in the order they were submitted. The time slice diagram for the above question is as shown:

Total time required for Process A:
145 + 11 + 145 + 11 + 145 + 11 +145 + 11 + 145 + 11 + 55 + 11 + 105 + 11 + 145 + 11 + 140 = 1258μS
Total time required for Process B:
145 + 11 + 145 + 11 + 145 + 11 +145 + 11 + 145 + 11 + 55 = 835μS
Total time required for Process C:
145 + 11 + 145 + 11 + 145 + 11 +145 + 11 + 145 + 11 + 55 + 11 + 105 = 951μS
Total time required for Process D:
145 + 11 + 145 + 11 + 145 + 11 +145 + 11 + 145 + 11 + 55 + 11 + 105 + 11 + 145 + 11 + 140 + 11 + 120 = 1389μS

Therefore, none of the processes met their timing requirements